The present invention relates to operations in flash memory devices. More particularly, the present invention relates to a method and apparatus to suspend an operation in a flash memory device.
Flash memory devices have proven to be important memory elements in the past several years, and industry pundits predict an ever-increasing role for such devices in the future. A great advantage flash memory devices have over typical eraseable programmable read only memories (EPROM""s) and electrically erasable programmable read only memories (EEPROM""s) are, respectively, system programmability and lower cost.
Despite the many advantages of flash memories over other memories, flash memory devices have several opportunities for improvement. For example, flash memories in their typical implementations suffer from the problems of xe2x80x9cover erasurexe2x80x9d and xe2x80x9cwild bitsxe2x80x9d which result in all bits not behaving exactly alike with respect to their electrical behavior. In fact, many flash memory devices include wide variations of electrical behavior between adjacent bits.
Designers of flash memory devices have developed very sophisticated schemes in order to resolve the problems related to bits having disparate electrical behavior. For example, a flash memory device during programing or erasing of the memory elements proceeds through a process of interrogating each memory element and evaluating the respective margins after the operation to determine whether it needs to be re-programmed or further erased. The individual treatment of memory elements has caused the logic circuitry associated with flash memories to become very complicated.
Memory arrays in flash memory devices typically must be programmed before they can be erased in order to avoid erasing bits into a very negative threshold and disturbing data in other bits during reading. Even during the cycle of programming, the device determines if the bits are sufficiently programmed. A unique verification cycle for an erase operation is performed. Some devices tighten the distribution of memory element threshold voltages after the erase operation for better manufacturability. The memory device also often determines, after the erase operation, whether the data in the memory array remains undisturbed. These procedures, as appreciated by those skilled in the art, are very sophisticated.
In order to perform such a sophisticated operation, an equally sophisticated state machine is often required. Simply put, a state machine can be a controller in a flash memory device or other integrated circuit. The state machine typically includes several steps that must be performed in the erase operation. This operation takes a relatively long period of time for the processors executing the steps, which could be in the order of seconds. Rather than necessarily occupying the processor during this time, a suspend command has been developed to permit the operation to stop itself and allow the processor to read an unaffected block of memory. In prior art flash memories, a suspend command was permitted only during certain predetermined steps in the operation of the state machine. Only certain cycles in the operation could be suspended, which itself proved difficult to implement. For example, if analog voltage generation or discharge was required, a suspended cycle would often prevent a state machine from functioning properly.
The consequence of a limited number of suspend operations had a deleterious effect on response time. In certain cases, the system was required to wait for up to 100""s of milliseconds to attain a suspendable cycle. Although the prior art suspend system proved to have a better response time than without a suspend command, much room for improvement was left for flash memories to achieve response times in the order of similar devices.
The present invention relates to a state machine and an associated method for achieving a faster response time for an interruption of an erase operation. In particular, the present invention is directed to a state machine having a plurality of interconnected execution cycles. The execution cycles include incremental cycles and other cycles. The state machine also includes a plurality of suspend cycles. Each suspend cycle is connected directly to one of the execution cycles. At least one of the suspend cycles is connected directly to one of the other cycles.